Application specific integrated circuit (ASIC) technology has undergone rapid changes in recent years. Current ASIC chips may include functional blocks, such as microprocessors, interfaces, memory arrays, and DSPs (digital signal processors) all of which need to be validated for design correctness and/or tested for manufacturing defects.
Microprocessor testing is typically considered one of the most complex problems in ASIC testing, whether the microprocessor happens to be an ASIC core or a stand-alone device. This is because modern microprocessors are highly complex and typically enhanced with additional operating modes and features. For example, newer ×86 microprocessors such as Pentium® processors as marketed by Intel® Corporation are designed to maintain software compatibility with previous 80×86 microprocessor generations (e.g., 8086/8, 80286, 80386, and 80486). These newer ×86 microprocessors include multiple operating modes and are equipped with cache memory systems and added hardware support features for operation in multi-processor environments. Errors in the designs of microprocessors and defects introduced during manufacturing may cause the microprocessors to produce incorrect results during operation.
Traditionally functional tests have been used to ensure that complex devices such as microprocessors under test produce correct results in all possible operating environments. Functional tests may be manually written by designers/programmers but are typically generated by random instruction test (RIT) tools, via a host computer under an operating system (OS) as described, for example, in the “Native Mode Functional Test Generation For Processors With Applications To Self Test and Design Validation” by Jian Shen and Jacob A. Abraham of the Computer Engineering Research Center, University of Texas, IEEE International Test Conference, pp. 990-999, August 1998. In general, these functional tests include software instructions which cause a microprocessor under test to perform a desired activity and to produce a test result. The test result is compared with an expected test result derived from a functional specification of the microprocessor under test. Any difference between the test result produced by the microprocessor under test and the expected test result represents a failure of the functional test. Such a functional test failure may indicate improper microprocessor operation due to a design error or a manufacturing defect.
However, manual development of functional tests is very costly in terms of the (human) resources needed. Likewise, RIT tools are not very efficient in terms of high fault coverage and, often, require a large number of tests and a large tester memory to produce high coverage. In addition, large scale, high pin count and expensive automatic test equipments (ATE) such as IC testers with several hundreds test pins (test channels), each of which includes a pattern generator, a timing generator and a frame processor, are required.
Other types of testing, such as design-for-test (DFT) techniques and built-in self-test (BIST) schemes such as scan, partial scan, logic BIST, and scan-based BIST, have been utilized to structurally test various logic blocks within a microprocessor. However, structural test tools require a large amount of test data and additional hardware area (extra logic circuits) to implement the test logic. In addition, there are inherent problems relating to high performance penalty and low collateral coverage.
Therefore there is need to develop a new tool programmed to generate a re-generative functional test in the form of a kernel that can be loaded on-board of a complex device such as a microprocessor to generate and execute its own functional tests in real time so as to avoid test data volume issues and achieve high collateral coverage with at-speed test application.